1. Field of the Invention
The present invention pertains to a shared RAM access arrangement, particularly an arrangement in which the shared RAM is electrically connected to a relatively slow bus controlled by a first microprocessor, and is also accessed by a second microprocessor which operates on a relatively faster bus.
2. Description of the Related Art
Shared RAM is a relatively common arrangement for permitting first and second (or more) microprocessors to communicate with one another. For example, it is now conventional for a first microprocessor to store a message or data in shared RAM, and for the second microprocessor to access the message or data in shared RAM for subsequent processing.
Microprocessors, and the buses to which they are connected, differ in both speed and bit width. These differences have caused difficulties in providing an access arrangement to shared RAM. For example, in a situation where shared RAM is electrically connected to a relatively slow microprocessor and address bus to be shared with a second microprocessor which is relatively faster. Likewise, difficulties are encountered when the address or data bus to which the shared RAM is connected has a different width from the address or data bus of the second microprocessor.
Various solutions have been proposed to permit access to shared RAM when the shared RAM is electrically connected to a bus which is relatively slower than the bus from which shared access is desired. Those solutions, however, are different from the invention herein.